(1) Field of the Invention
The present invention relates to semiconductor devices, and more specifically to a process for fabricating high density dynamic random acess memory, (DRAM), devices.
(2) Description of Prior Art
A major criteria for high density dynamic random access memory, (DRAM), devices, is the ability of the storage node of this device, to supply the desired capacitance needed for circuit performance. The basic DRAM memory cell is usually comprised of a transfer gate transistor and a connected capacitor. Charges are stored in the capacitor section of the DRAM, and are accessed via the transfer gate transistor. The ability to densely pack storage cells, while maintaining sufficient stored charge, is a function of the type and structure of the capacitor section of the DRAM. One method, used in the industry, for capacitors is the "stacked storage cell" design. In this design two conductive layers, such as polycrystalline silicon, are placed over a section of the transfer gate transistor, with a dielectric layer sandwiched between the polycrystalline layers. Cells constructed in this manner are referred to as stacked capacitor cells, (STC).
As DRAM densities increase, resulting in smaller device dimensions, the ability to maintain adequate capacitance using the STC structure becomes difficult. The shrinking dimensions of the transfer gate transistor limits the dimensions of the capacitor plates, thus severely limiting the ability to maintain the capacitance needed to operate the DRAM. Alternatives for maintaining signal, capacitance, include decreasing the thickness of the dielectric layer of the STC structure. However it is difficult to decrease the dielectric material much below about 100 Angstroms, in silicon dioxide equivalent, without raising yield concerns. Therefore the industry has attempted to maintain capacitance by increasing the area of the conductive plates, even when the underlying access area, transfer gate transistor region, is decreasing in dimension. This is accomplished by a process producing concaves and convexes on the surface of the lower electrode, thus creating increased surface area, without increasing the overall dimension of the DRAM cell. In U.S. Pat. No. 5,290,729, Hayashide, etal, describe a process for producing roughened storage node layers of polycrystalline silicon by using specific deposition conditions and subsequent POCl3 and oxidation processes. Also Fazen, etal, in U.S. Pat. 5,278,091, describe a different form of roughened polysilicon, used for the storage node. However in the invention now disclosed the level of roughness, needed to adequately complement the decreasing DRAM cell dimension, is dramatically increased via specific and unique processing methods.